Slave Communication Interface

When the ASIC operates in SPI mode, it is an SPI slave and activated through the SSELn pin (active low). The Slave Select should be taken high between each SPI transaction, and SPI transactions are ignored if the slave is not selected. SPI is a synchronous communication protocol clocked by SCLK which is driven by the master. SCLK should idle low. Both the master and the slave will change the data on the rising edge of clock and sample it on the negative edge of clock (CKPOL=0 and CKPHA=1).

When not enabled the MISO pin will be driven high. Data packets are 16 bits and MSB is transferred first.