# Qwantum ASIC Registers This section describes the register addresses and values that may be accessible in read/write by the SPI master. ## Register Map ## **Table - Register Map**


Group	Lower Addr Range	Upper Addr Range	Number of Data Words	Access Type	Description	Default Value
User Registers	0x00	0x00	1	R/W	Configuration Register	0x0000
User Registers	0x01	0x01	1	R/W	FSM State Command Register	0x0000
User Registers	0x02	0x02	1	R	Status 1 Register	0x2000
User Registers	0x03	0x04	2		Reserved
User Registers	0x05	0x05	1	R/W	Acknowledge Register	0x0000
User Registers	0x06	0x09	4		Reserved
EEPROM Shadow Registers	0x0A	0x0A	1	R/W	MagTek Password Register	0x0000
EEPROM Shadow Registers	0x0B	0x0F	5		Reserved
EEPROM Shadow Registers	0x10	0x10	1	R	ASIC C Test Revision Code Register
EEPROM Shadow Registers	0x11	0x18	8		Reserved
EEPROM Shadow Registers	0x19	0x1C	4	R	Security Certification Code Register
EEPROM Shadow Registers	0x1D	0x1D	1	R	Program Lock C Read Security Lock Register
EEPROM Shadow Registers	0x1E	0x1F	2		Reserved
Reserved	0x30	0x7F	80		Reserved

## User Registers ## **Table - Configuration Register (address = 0x00)**


Bit	Name	Description
15	QT_DIS	Qwantum Token Disable = 0; Enable Qwantum Token = 1; Disable Qwantum Token
14	QTEXT_DIS	Qwantum Token Extended Mode Disable = 0; Enable Qwantum Token Extended Mode = 1; Disable Qwantum Token Extended Mode (Standard Mode)
13	TKA_DIS	Track A Disable = 0; Enable Track A = 1; Disable Track A
12		Reserved
11	TKC_DIS	Track C Disable = 0; Enable Track C = 1; Disable Track C
10	IRQ_DIS	Card Present Interrupt Request Disable = 0; MISO pin signals the microcontroller for both card present detection and data ready = 1; MISO pin only signals the microcontroller for data ready
9		Reserved
8	OBFUSCATION_DIS	Obfuscation Disable = 0; Enable Obfuscation = 1; Disable Obfuscation
7:0		Reserved

{% hint style="info" %} **NOTES:** The Configuration register may be accessed in write only when FSM\_STATE\_STATUS\[2:0]=OFF, ATR or WAKEUP. If the SPI master sends the write command for the Configuration register when FSM\_STATE\_STATUS\[2:0] is not OFF or ATR or WAKEUP, then the command will be disregarded. {% endhint %} ## **Table - FSM State Command Register (address = 0x01)**

Bit

Name

Description

15:12

FSM_STATE_CMD[3:0]

Finite State Machine State Command

When the SPI command is Write Register Command WREG:

= 0001 then FSM State moves to OFFSET CORRECTION state. When the offset correction is complete, the state machine will move on to the OFF state. The command is valid only if the FSM is in the OFF state or in the ATR state. The FSM state can be obtained reading the Status 1 Register (address=0x02): FSM_STATE_STATUS[3:0].

= 0010 then FSM State moves to OFF state. The command is valid only if the FSM is in the EXTRACT or ATR state. The FSM state can be obtained reading the Status 1 Register (address=0x02): FSM_STATE_STATUS[3:0].

= 0110 then FSM State moves to ATR state. The command is valid only if the FSM is in the OFF or EXTRACT state. The FSM state can be obtained reading the Status 1 Register (address=0x02): FSM_STATE_STATUS[3:0].

11:0

Reserved

## **Table - Status 1 Register (address = 0x02)**

Bit

Name

Description

15:12

FSM_STATE_STATUS[3:0]

Finite State Machine Status:

= 0000; Status = POR/RESET

= 0001; Status = OFFSET CORRECTION

= 0010; Status = OFF

= 0011; Status = DIGITAL_OFFSET_CORRECTION

= 0100; Status = MPR_COPY

= 0101; Status = SWIPE

= 0110; Status = ATR

= 0111; Status = WAKEUP

= 1100; Status = EXTRACT

= 1101; Status = ERASEMEM

= 1111; Status = ERASEMEM

PAIR_STATUS

Determine if the microcontroller is paired with Qwantum ASIC

= 0; Not paired

= 1; Paired

PROG_LOCK_STATUS

Determine if EEPROM programming is locked

= 0; Not locked

= 1; Locked

READ_LOCK_STATUS

Determine if EEPROM read is locked

= 0; Not locked

= 1; Locked

DIRECTION

Card swipe direction

= 0; Forward

= 1; Reverse

7:0

Reserved

## **Table - Acknowledge Register (address = 0x05)**

Bit

Name

Description

15:1

Reserved

IRQN_ACK

IRQn Acknowledge

When the MISO pin signals the microcontroller of a card present condition, writing a 1 to this bit will clear the MISO pin until data ready.

## **Table - MagTek Password Register (address = 0x0A)**

Bit

Name

Description

15:0

MAGTEK_PASSWORD[15:0

]

MagTek Password Register

MagTek may enter in test mode by writing the MagTek Password Register with the value 0x7A53.

In MagTek test mode the customer has access to some EEPROM shadow registers.

Register address = 0x11 is available in Read/Write. This feature should be used only for debug. Security Certification Code Registers (addresses = [0x19 ~ 0x1A]) are available in

Read for allowing the pairing between the device and the microcontroller.

## EEPROM Shadow Registers ## **Table - Test Revision Code & ASIC Revision Code Register (address = 0x10)**


Bit	Name	Description
15:12	EE_ASIC_MAJ[7:4]	Major Silicon Revision for All Layers
11:8	EE_ASIC_MIN[3:0]	Minor Silicon Revision for Metal Layers only
7:0	EE_TEST[7:0]	Test Revision

## Table - Security Certification Code Register (address = \[0x19 \~ 0x1C])

Bit

Name

Description

15:8

EE_PAIRING_CODE[63:0]

Security Certification Code Register

The code is 8 bytes (64 bits) width. The code shall be unique from die to die and is generated at tester level. The code can be read only in MagTek test mode or Manufacturer test mode. The code allows to pair the device with the microcontroller. The pairing happens if the SPI master writes the Security Certification Code Register with the value stored in the register. The write does not take place. The write value is used only to compare it with the value stored in the register.

## **Table - Program Lock & Read Security Lock Register (address = 0x1D)**

Bit

Name

Description

15:8

EE_PROG_LOCK_CODE[7: 0]

NVM Program Lock Code Register

Once the NVM Program Lock Code register is written with the value 0xFF then the EEPROM is no longer programmable: the NVM may still be read but will not be programmable. This behavior prevents accidental reprogramming.

7:0

EE_READ_LOCK_CODE[7: 0]

NVM Read Lock Code Register

Once the NVM Read Lock Code Register is written with the value 0xFF then the NVM is no longer readable. The customer has to enter into MagTek test mode to read the Security Certification Code Register in order to pair the device with

the microcontroller.

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