Ctrlk
For the complete documentation index, see llms.txt. This page is also available as Markdown.

Qwantum ASIC Configuration

When the ASIC is powered on or reset, it enters the OFF state. After the ASIC is paired with the microcontroller, the microcontroller firmware can check the current state of the ASIC and move the ASIC to the OFF state if it is not already in the OFF state.

Once the ASIC is paired with the microcontroller, it needs to be configured by updating the following bits in the Configuration register. The power-on default value of the configuration register is 0x00.

Table - Qwantum ASIC Configuration - Configuration Register (address = 0x00)

Bit

Name

Description

15

QT_DIS

Qwantum Token Disable

= 0; Enable Qwantum Token

= 1; Disable Qwantum Token

14

QTEXT_DIS

Qwantum Token Extended Mode Disable

= 0; Enable Qwantum Token Extension mode

= 1; Disable Qwantum Token Extension mode (Standard Mode is enabled)

13

TKA_DIS

Track A Disable

= 0; Enable Track A

= 1; Disable Track A

12

Reserved.

11

TKC_DIS

Track C Disable

= 0; Enable Track C

= 1; Disable Track C

10

IRQ_DIS

Card Present Interrupt Request Disable

= 0; MISO pin signals the microcontroller for both card present detection and data ready

= 1; MISO pin only signals the microcontroller for data ready

9

Reserved

8

OBFUSCATION_DIS

Obfuscation Disable

= 0; Enable Obfuscation

= 1; Disable Obfuscation

7:0

Reserved

Track B

Unlike Track A and C, Track B cannot be disabled.

Obfuscation of Encoded Card Data

In SPI mode, Track F2F data from enabled channels and the Qwantum Token can be obfuscated during the EXTRACT state as it’s read out of the ASIC, using an obfuscation algorithm. This updated algorithm is not described in this specification. In SPI mode, the obfuscation can be disabled by the configuration register. In Data Strobe mode, the obfuscation is always disabled.

Non-Interrupt (Polling)

The microcontroller firmware puts the QASIC in the ATR state to make the ASIC ready for a card swipe. The firmware can find out if new card data is ready for read in the ASIC by reading the current state of the ASIC via the Status 1 register (address = 0x02). The ASIC enters the EXTRACT state when new card data becomes available after a card is swiped. Thus, the microcontroller firmware should poll the Status 1 register in a loop until the current state becomes the EXTRACT state.

Interrupt

The QASIC (SPI slave device) should be released (SSELn on the ASIC should be held high) by the SPI master to detect an interrupt from the ASIC. When the card present interrupt request in the ASIC is enabled, the MISO pin is used to signal the start of a card swipe and the card data ready to the microcontroller.

Qwantum ASIC provides two different options for using interrupts.

  • Card Data Ready interrupt only (bit [10] (IRQ_DIS) of the Configuration register is set to 1)

  • Card Present Interrupt Request and Card Data Ready interrupt (bit [10] (IRQ_DIS) of the Configuration register is set to 0)

When the QASIC is inactive (SSELn is high), the MISO pin on the ASIC is used to signal the microcontroller when data is available to be shifted out. Optionally, it can be used to signal the start of a card swipe (the card present condition) to allow the microcontroller more time to wake up when the Card Present Interrupt Request is enabled. When neither condition is present, the MISO pin is held high.

Card Present Detection is enabled when bit [10] (IRQ_DIS) of the Configuration register (address = 0x00) is 0. If Card Present Detection is enabled, when the SWIPE state is entered then the MISO pin will be set low to indicate a wake-up event (Card Present, or ‘CP’ in the waveform below) for the microcontroller. The MISO pin will be held low until the microcontroller writes IRQN_ACK=1 (bit [0] of the Acknowledge register (address = 0x05)).

Note that while the microcontroller is writing the ASIC registers, SSELn will be low, and MISO will act as a SPI pin, and not continue to signal the card present/data ready state.

When data is ready to be transferred, the MISO pin should be set low and remain low until the microprocessor issues one of the Read Track Commands or the Reset Command. As this condition is cleared by retrieving the data or a reset, there is no need to clear IRQN_ACK bit in the Acknowledge register for this condition.

Note that if the Data Ready condition is reached before the microcontroller completes writing the Acknowledge register after a Card Present Detection, the MISO pin will be set low immediately upon the rising edge of SSELn.

Card Present / Data Ready Signal

It is very common that SPI MISO pin on the microcontroller is multiplexed with GPIO. In that case, the MISO/GPIO pin can be configured as GPIO while waiting for card present interrupt or card data ready interrupt. After the interrupt is detected, the multiplexed pin can be re-configured as MISO and the SSELn pin is held low so the microcontroller firmware can access the ASIC’s user registers to check the status of the ASIC and read card data from the ASIC. The pin can be changed back to GPIO after finishing the user register access.

In addition to controlling the MISO/GPIO pin configuration and the ASIC interrupt setting, the processor interrupt for the GPIO should be enabled and the interrupt service routine for the GPIO should be available.

The microcontroller and Qwantum ASIC should be configured as follows to use the Qwantum ASIC interrupt.

  • Interrupt for SPI/GPIO in the microcontroller should be correctly configured and enabled.

  • The card present interrupt should be enabled in the ASIC configuration register if it is required. Otherwise, only the card data ready interrupt can be used.

  • The ASIC should be inactive (SSELn is released or held high by the SPI master) to generate interrupts.

Last updated